1. Field
The present invention relates to multiprocessor data processing systems and, more particularly, to cache techniques that facilitate transitioning between lockstep and non-lockstep modes of processor operation.
2. Related Art
In some data processing applications, multiple processor instances are employed to concurrently execute identical code sequences with identical data inputs. Typically, the processors execute in lockstep. Error logic may then detect a difference in execution states of the processors and, based thereon, signal a transient or permanent error in one of the processor instances. For example, in automotive electronics systems, this form of redundancy can be used to achieve reliability thresholds or desired safety integrity levels. Unfortunately, providing redundant processors can be expensive and, as a general proposition, not all aspects of a data processing application require such reliability or safety integrity levels. As a result, non-critical aspects of a data processing application may be burdened by lockstep execution overheads and/or otherwise useful processing cycles may be squandered.
Persons of ordinary skill in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.